Senior System Verilog Verification Engineer - Cambridge, United Kingdom - Platform Recruitment
Description
Senior System Verilog Verification Engineer - Cambridge - Negotiable
I am currently recruiting for a senior system Verilog verification engineer for a client of mine that specialise in machine learning & AI inference solutions.
Key responsibilities:
- Designing System Verilog based verification environments to support a
- Optimizing verification code to enable fast simulation support for software
- Communicating the verification environment design and supporting others
Key skills:
- Strong understanding of Verilog
- Experience simulating and verifying large RTL designs
- Experience working in Linux based development environments
- Knowledge of C/ C or other imperative coding language
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