Bartolome Ebalobo

Background
On 2005, I earned my bachelor’s degree in Electronics Engineering and immediately
my first Analog Layout experience in ROHM, Philippines. Thereon, I joined the layout
sourcing company and was assigned to MediaTek, Institute of Microelectronics,
Cypress, Intel, Dialog Semi and after acquired by Renesas.

Experience
For more than 15 years, I have participated in Chip development with different
foundries like TSMC, Globalfoundries, UMC, Xfab, Novuton, Vanguard and Dongbu,
ranging from 350nm down to 10nm and 14nm Finfet technology.
With Renesas, my learning is still on top. I am proficiently having a hands-on
experience with the latest Virtuoso Studio Layout editor IC23.1, P2P extraction (R3D Draw and R3D)
for electromigration and hotspot analysis, Synopsys Custom compiler layout editor,
Synopsys StarRC and Calibre Quantus RC, Conly and Ronly parasitic extraction
tools and noise-sensitive analysis.

• Main chip top layout designer of complex circuits. pad-ring placement, bonding diagram creation, hierarchical layout integration, chip size estimation
• Analog top: analog layout block design - integration of analog sub-block hierarchy.
• Analog layout of circuit function: Comparator, Op-Amp, Bandgap, Amplifiers, ADC, DCDC, Oscillator, Low Drop Out, Phase Lock Loop, Biasgen, etc.
• Digital top: abstract generation, LEF creation, power and ground mesh.
• Integration of Digital top and Analog top in mixed signal chip design.
• Generate dummy fillers to debug density errors of OD/ active/ diffusion, Poly silicon and metal layers.
• Provide extracted view RC, Ronly and Conly using Calibre PEX to my circuit engineer.
• Perform initial and final layout design review with circuit designers.
• Verification and Debugging of Calibre reports: DRC, LVS, Antenna, ERC , minimum and maximum density error and other reliability checks.
• Proficient in TSMC BCD mixed signal Deep-Nwell layer to separate sensitive NMOS transistors from Substrate and Digital top noise.
• Proficient in SOI process, ultra thin buried oxide layer, Pwell layer, STI- silicon trench isolation and DTI-deep trench isolation for latch-up prevention.
• Especially in RF Layout: noise isolation techniques such as shielding, reverse bias guard-ring, Isolation ring, de-coupling, etc.
• Understanding RC delay, electro-migration, self-heating, and cross capacitance.
• Debug noisy and sensitive lines from simulations results.
• Power MOS, ESD devices , IO cell layout.
• Extraction/ Reduction of parasitic resistance, capacitance using R3D, Silicon Frontline
• Debugging of Electro-migration and current crowding hotspot using R3D draw analysis.
• Analog layout matching structures: common centroid, inter-digitation, etc.
• Matching structures: differential pair common centroid, current mirror, cascoded current mirror, voltage divider resistors interdigitation.
• Understanding the basic electronic principle of basic CMOS device theories, cross-sectional view, voltage drop that can trigger latch-up in PN junction, heat
or noise dissipation on the substrate, biasing: reverse and forward bias.
• Knows the principle of noise consideration especially in RF chip designs.
• Knows the principle of failure mechanism prevention such as Latch up, Electro-migration, Design for Manufacturability, Electro-static devices, Well Proximity
effect, Length of Diffusion, Shallow trench isolation, Antenna violation, Body effect.
• Help other Layout group, individual contributor, mentoring junior layouter.
• Help tape-out procedure and documentation.
• Help circuit engineer optimize the circuit and layout.

Bachelor in science for Electronics and Communications Engineering | Technological Institute of the Philippines | 31/05/2000 – 13/04/2005