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- 4+ years experience in IP level verification
- Excellent command of System Verilog
- Experience with UVM
- Owning a CPU project and developing it through all stages of the verification process
- Production of verification strategies and test plans
- Determining causality of problems in the verification process
Senior Verification Engineer - Cambridge, United Kingdom - European Recruitment
Description
Job Description
Verification Engineering opportunity with a globally prestigious semiconductor company at their HQ in Cambridge, at senior and staff levels of seniority.
A Verification Engineer must have:
Responsibilities include:
If you would be interested in this role, email your CV to - or apply directly via LinkedIn
This role is able to provide visa and relocation support from anywhere in the world
Key Words: Verification Engineer / Verification / UVM / Semiconductor
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