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    Principal Design Verification Engineer - Cambridge, Cambridgeshire, United Kingdom - Fast Forward

    Fast Forward
    Fast Forward Cambridge, Cambridgeshire, United Kingdom

    Found in: Jooble UK O C2 - 1 day ago

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    Description
    Senior / Principal Design Verification Engineer

    In this role you will have the opportunity to apply industrial-strength design verification to high quality open source code bases.

    We are raising the bar for verification of open source projects to meet the highest commercial standards. Design, implement and debug block-level and system-level tests and testbenches using SystemVerilog and UVM
    Actively review contributions to our open source projects
    Triage and debug nightly regressions
    Contribute to the ongoing design and development of our test and continuous integration infrastructure
    Collaborate with partners to author papers for academic and industry conferences
    5 years+ prior industry experience of design verification including significant SystemVerilog and UVM usage
    Experience across the full verification cycle from initial planning to final tapeout
    Confident providing work estimates and coordinating work with a project manager
    Undergraduate degree in a technical discipline or equivalent experience
    Understanding of security countermeasures against attacks such as fault injection or side-channel analysis
    Programming using C and/or Python in tests and automation
    Experience with leading a team or being a primary technical contributor in a major project

    Five years ago, lowRISC (a community interest company) took up the challenge of helping to bring the world's first commercially viable, collaborative, open source silicon root of trust (RoT) design, OpenTitan, to market.

    We didn't want to create a 'one-and-done monolith' though — instead, we set out to use the project as the proving ground for our general development framework: the Silicon Commons.

    This innovative workflow merges open source software development best practices with an industrial-strength chip design methodology, enabling the creation of reusable, high quality silicon IP by our diverse coalition of corporate and academic partners including Google, ETH Zurich, G+D Mobile, Nuvoton, Rivos, Seagate, Western Digital and Winbond.

    Join us and be part of a company positively changing the future of silicon design.
    lowRISC offers a generous benefits package including:
    ~ Competitive salary within the range of £61,000 - £94,000

    Do you require visa sponsorship?*
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