- Strong knowledge of hardware verification languages (SystemVerilog) along with assembly, C/C++ and scripting.
- Experience in various verification methodologies, ideally UVM.
- Exposure to all stages of verification including requirements collection, test plans, testbench implementation, test case development etc.
- Experience with complex IP / block / module level designs.
- Fluency in English.
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Senior Verification Engineer - Cambridge, Cambridgeshire, United Kingdom - European Recruitment
Description
Job DescriptionSenior Verification Engineer (UVM)
We are working with a world-leading technology company who are looking to grow their team in Cambridge, UK with experienced Verification Engineers.
This will be a full-time permanent position, offering above market compensation, and where required we can provide relocation and visa support.
You will play a key role in developing hardware verification testbenches for next-gen hardware IP. In particular, we are looking for individuals with experience of complex IP / module level designs.
The successful candidate should demonstrate the following: