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Handsworth

    Principal Design Engineer - Ashley Down, United Kingdom - ARM

    ARM
    ARM Ashley Down, United Kingdom

    1 week ago

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    Description

    Job Overview:

    ARM's hardware plays a crucial role in the ongoing digital transformation that is reshaping our lifestyles and the way businesses function.

    This exciting opportunity is ideal for a skilled and motivated design engineer to join the dedicated System IP team.

    This dynamic role involves utilizing cutting-edge hardware design methods to create sophisticated and adaptable hardware IP solutions for Arm-based Systems.

    The Interconnect team specializes in developing the Arm Corelink Interconnect IP family. These Interconnects and NoCs are engineered for intelligent connected systems in diverse sectors like mobile, IoT, networking infrastructure, and automotive industries. The scalable IP is optimized for AMBA-compliant SoC connectivity and can be tailored for various performance levels.

    Responsibilities:

    • Analyze proposed specifications to identify implementation challenges and opportunities, collaborating with architects to enhance and fine-tune concepts
    • Plan, monitor, and synchronize tasks for yourself and your team
    • Collaborate with modeling, verification, performance analysis, and back-end implementation colleagues to ensure your design meets all functional and performance criteria
    • Enhance design methodologies to align with evolving requirements

    You will lead the development of one or more functional blocks of the IP. Demonstrate a comprehensive grasp of all aspects related to successful product delivery, including expertise in low-power design techniques, understanding the impact of design choices on system performance, proficiency in creating area-efficient designs, and employing verification techniques for innovative and high-quality outcomes.

    Required Skills and Experience:

    • Demonstrated track record of delivering high-quality, low-power, high-performance sophisticated micro-architecture and RTL designs using System Verilog, Verilog, or VHDL within reasonable timelines
    • Ability to navigate and make strategic design trade-offs at a high level and articulate the reasoning behind those decisions
    • Familiarity with ASIC (or FPGA) design methodologies, IP signoff procedures, with a deep understanding of timing/area/complexity trade-offs in complex data path designs

    'Nice To Have' Skills and Experience:

    • Experience in team leadership and mentoring
    • Proficiency in memory system interconnect protocols (e.g. AMBA ACE-Lite or AXI)
    • Strong grasp of SystemVerilog Assertions (SVA) and formal verification
    • Proficiency in a scripting language such as Perl, Tcl, C shell, Python
    • Knowledge of various hardware verification languages such as SystemVerilog
    • Prior involvement in Functional Safety product development for the Automotive market (adhering to standards like ISO 26262 and/or IEC 61508)

    In return -

    By leveraging your engineering expertise, you will contribute to advancing technologies and impacting the functionality of millions of devices for years to come.

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